Parameterized interface passing through uvm_config_db

UVM
,
4

In reply to dave_59:

dave, thanks for you relay

but I run a test as the following

//param_pkg.sv


package param_pkg;
	parameter n=8;
endpackage

//param_if.sv


import param_pkg::*;
interface param_if;
	logic [n-1:0] data;
	logic [n-1:0] addr;
endinterface

//top_tb.sv


module top_tb;

import uvm_pkg::*;
`include "uvm_macros.svh"
`include "param_if.sv"

param_if my_param_if();
dut dut_inst(
...);

initial begin
   uvm_config_db #(virtual param_if)::set(null, "uvm_test_top",                "vif", my_param_if);
run_test();
end

endmodule

//mycase0.sv


class my_case0 extends base_test;
   `uvm_component_utils(my_case0)
	virtual param_if param_if;

   function new(string name = "my_case0", uvm_component parent = null);
	//function new(string name, uvm_component parent);
      super.new(name,parent);
   endfunction 
   extern virtual function void build_phase(uvm_phase phase); 
   extern virtual function void connect_phase(uvm_phase phase); 

    task run_phase(uvm_phase phase);
	begin
               my_rst_seq my_seq= my_rst_seq::type_id::create("my_seq",this);
		phase.raise_objection(this,"rst_ctrl_seq active");
		my_seq.start(env.i_agt.m_sqr);
                 phase.drop_objection(this,"rst_ctrl_seq finished");

	end
endtask : run_phase	

endclass

function void my_case0::build_phase(uvm_phase phase);
   super.build_phase(phase);
       if(!uvm_config_db#(virtual param_if)::get(this,"","vif",param_if))
	`uvm_info("my_case0","error",UVM_MEDIUM)

endfunction

/////////////////////
I get the following error:

** Error: (vsim-13216) Illegal assignment to type ‘virtual param_if’ from type ‘interface param_if #()’: Vir. ‘param_if’ interface must be assigned a matching interface or virtual interface.

Time: 0 ps Iteration: 0 Instance: /top_tb File: ./top_tb.sv Line: 59

the simulator is questasim 64 2019.2_2

can you correct me, thanks!!!