Parameterized interface passing through uvm_config_db

In reply to chr_sue:

here is the package


package rst_agent_pkg;
   `include "uvm_macros.svh"
   import uvm_pkg::*;
	 import test_pkg::*;
 
   `include "rst_item.sv"
   `include "rst_agent_cfg.sv"
   `include "rst_item_drv.sv"
   `include "rst_item_mon.sv"
   `include "rst_agent.sv"
   `include "seq_lib/rst_seq_lib.sv"
	 `include "rst_env.sv"
	 `include "base_test.sv"
	 `include "my_case0.sv"
//////////////	`include "rst_if.sv"
 
endpackage: rst_agent_pkg

////compile.do
quit -sim
rm -rf work
vlib work

vlog -timescale “10ps/10ps”
+incdir+./…
…/test_pkg.sv
./param_pkg.sv
./rst_agent_pkg.sv
./dut.sv
./top_tb.sv

vopt +acc top_tb dut -o opt

vsim
+UVM_TESTNAME=my_case0
+UVM_NO_RELNOTES
+UVM_TIMEOUT=100000000
-classdebug -uvmcontrol=all
opt

run 0