Parameterized assertions(SVA) - Bit wise using generate block

SystemVerilog
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3

In reply to dave_59:

Hello Dave,
Thank you very for your quick response

I have some questions regarding above reply,

  1. Is there no need to keep for loop in generate block.
  2. I didn’t understand the syntax which have used for rdata[i*8+:8], Is it same like this rdata[7(i+1)+i : 7(i)+i]**.