Parameterized assertions(SVA) - Bit wise using generate block

SystemVerilog
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2

In reply to kolliparapavankumar:

There is no need for [7:0] in your property. You can just write

property example(byte_vector_range, parity);
		@(posedge clk) disable iff (rst_n !== 1) 
		rdata_valid  |-> (^(byte_vector_range == parity);		
endproperty: example
 
for(genvar i=0;i<=((DATA_WIDTH/8)-1);i++) 
  pcheck: assert property (example(rdata[i*8+:8],rdata_parity[i]))
  else $error("Data not matched");