// DATA_WIDTH = 32/64/128
property example(byte_vector_range[7:0], parity);
@(posedge clk) disable iff (rst_n !== 1)
rdata_valid |-> (^(byte_vector_range[7:0]) == parity);
endproperty: example
generate
for(genvar i=0;i<=((DATA_WIDTH/8)-1);i++) begin
assert property (example(rdata[7*(i+1)+i : 7*(i)+i],rdata_parity[i]))
else $error("Data not matched");
end
endgenerate
I am getting error for above assertion, Can I use like this if not please suggest me a way
Error is:
Error-[SE] Syntax error
Following verilog source has syntax error :
"src/assertions/assertions.sv",
595: token is '['
property example(byte_vector_range[7:0],
parity);
^
In reply to kolliparapavankumar:
There is no need for [7:0] in your property. You can just write
property example(byte_vector_range, parity);
@(posedge clk) disable iff (rst_n !== 1)
rdata_valid |-> (^(byte_vector_range == parity);
endproperty: example
for(genvar i=0;i<=((DATA_WIDTH/8)-1);i++)
pcheck: assert property (example(rdata[i*8+:8],rdata_parity[i]))
else $error("Data not matched");
In reply to dave_59:
Hello Dave,
Thank you very for your quick response
I have some questions regarding above reply,
- Is there no need to keep for loop in generate block.
- I didn’t understand the syntax which have used for rdata[i*8+:8], Is it same like this rdata[7(i+1)+i : 7(i)+i]**.
In reply to kolliparapavankumar:
These are both features introduced in Verilog-2001. generate/endgenerate are optional. The compiler can figure it out without them.
Lookup indexed part selects in the LRM. It has the same behavior as what you wrote.