Parameteri override not working when used as typedef in lower level modules

SystemVerilog
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1

Hi,
I have a top level module where Im using a parameter value of 28. In the first instantiation when I use the parameter value it takes effect although Im using a different number (14 in this case) within the module it gets overriden to 28 which is what I expect but when i go one level down further and use the same parameter but Im using a typedef in this case I see 14 instead of 28 is this expected?.

Here is the code
top module:

module top (
....
...

peci #(
       .XXTOR_PECI_DATA_BYTES_LEN(28)
....
);

First level instantiation:

module pcei (
....

parameter XXTOR_PECI_DATA_BYTES_LEN   = 14;
parameter XXTOR_PECI_DATA_BITS_LEN = 8*XXTOR_PECI_DATA_BYTES_LEN;

logic [XXTOR_PECI_DATA_BITS_LEN -1:0] TxBuffer;

In this case I see TxBuffer is 224 bits wide

One level down:

parameter XXTOR_PECI_DATA_BYTES_LEN   = 14 ;
parameter XXTOR_PECI_DATA_BITS_LEN = 8*XXTOR_PECI_DATA_BYTES_LEN;



typedef reg [XXTOR_PECI_DATA_BITS_LEN -1:0] t_peci_xtor_tx_buffer ;

I see t_peci_xtor_tx_buffer is 112 bits (8*14) rather than 222 bits wide. Is it because Im using a typedef here?.

Thanks,
Sid

2

In reply to Sid85:

Since you did not show enough code, I’m guessing you need pass the override down the hierarchy. The override at the first level is not recursive.

3

Hi Dave,
My question is typedef preventing the override from happening at the lower level module. Im using the same parameter value in the lower level as the first level (14) but the only difference is typedef so Im wondering if this is a system verilog restriction on parameter override for typedef?.

SOrry Im unable to share a lot of code.

Thanks,
Sid

4

In reply to Sid85:

The use of a parameter in a typedef, or in any other construct should not prevent an override.

Did you override the parameter in the second level instantiation?


module top (
....
...
 
peci #(
       .XXTOR_PECI_DATA_BYTES_LEN(28)
....
);
...
endmodule

module pcei (
....
 
parameter XXTOR_PECI_DATA_BYTES_LEN   = 14;
parameter XXTOR_PECI_DATA_BITS_LEN = 8*XXTOR_PECI_DATA_BYTES_LEN;
 
logic [XXTOR_PECI_DATA_BITS_LEN -1:0] TxBuffer;

// code you did not show
second_level_module #(.XXTOR_PECI_DATA_BYTES_LEN(XXTOR_PECI_DATA_BYTES_LEN)))...

endmodule

module second_level_module(...);
// end code you did not show

parameter XXTOR_PECI_DATA_BYTES_LEN   = 14 ;
parameter XXTOR_PECI_DATA_BITS_LEN = 8*XXTOR_PECI_DATA_BYTES_LEN;
 
typedef reg [XXTOR_PECI_DATA_BITS_LEN -1:0] t_peci_xtor_tx_buffer ;
5

Hi Dave,
Thanks. I have the parameter set to 14 in the second level but at the top level it is set to 28 so it should override my setting in the second level instantiation but it doesnt for some reason.

6

In reply to Sid85:

You haven’t answered my question: Did you override the parameter in the second level instantiation? Meaning there needs to be two overrides as I showed you in my example.