Parameteri override not working when used as typedef in lower level modules

SystemVerilog
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3

Hi Dave,
My question is typedef preventing the override from happening at the lower level module. Im using the same parameter value in the lower level as the first level (14) but the only difference is typedef so Im wondering if this is a system verilog restriction on parameter override for typedef?.

SOrry Im unable to share a lot of code.

Thanks,
Sid