Parameter and generate usage in the interface

SystemVerilog
, ,
2

In reply to megamind:

We can use conditional generate statement inside generate loop. We can create the instance of monitor_if based on the value of ENABLE_DISABLE inside a for loop. The below code will iterate NUM_OF_INTERFACES times and it will check the value of ENABLE_DISABLE for each iterator value.

module top();
  
parameter NUM_OF_INTERFACES=5;
parameter ENABLE_DISABLE=0;
  
  genvar i;
  generate
    for(i=0;i<NUM_OF_INTERFACES;i++) begin: GEN_BLOCK
      if(ENABLE_DISABLE) begin: GEN_EN_BLOCK
        checker_interface monitor_if();
      end // if
    end // for
  endgenerate
endmodule

Alternatively, we can first check the value of ENABLE_DISABLE and then start the loop. This is same as 2nd point in your code.

module top();
  
parameter NUM_OF_INTERFACES=5;
parameter ENABLE_DISABLE=0;
  
  genvar i;
  generate
    if(ENABLE_DISABLE) begin: GEN_EN_BLOCK
      for(i=0;i<NUM_OF_INTERFACES;i++) begin: GEN_BLOCK
        checker_interface monitor_if();
      end // for
    end // if EN_DIS
  endgenerate
endmodule

Refer to IEEE 1800-2012 Section 27.5 for more information.