Hello all ,
In my design I need to verify that writing 1’s my register REG1 will update some internal signals of my design “sig1” and “sig2” … “sign”
the problem is that these signals are not top-level I/O of my DUT .
I need to reach these signals and check them , so what is the best way to do that in a uvm testbench?
can I create wire signals in my interface and assign to them these signals using the hierarchichal path?
ps:the signals I want to reach are inputs & outputs of my submodule.
thank you for your help.
In reply to dave_59:
thank you for your feedback Dave,
I read your paper but still it is not clear for me how to implement the solution.
I read in your paper the following : “you can use either the virtual interface
or abstract class mechanisms to reference the interface.” while in the example provided you used both abstract class and an interface.
also would you please explain to me :what do you mean by concrete class definition ?
I am not sure I understood what is the probe class you created for.
In reply to verif_25:
Here is another page explaining the same concepts.
The bind construct is used to insert a “probe” into the a sub-module of your DUT without having to make hierarchical reference crossing module boundaries.
The abstract/concrete class mechanism is an alternative to using virtual interfaces and is a separate concept from the bind construct. One advantage of the abstract class mechanism over the virtual interface mechanism is that it decouples parameterization of the actual interface to just the parameters (if any) required by the abstract class.
But use whichever mechanism is clear for you to understand.