Need SV Assertion to trigger once per signal edge

[modisidd]

Hello,

I am trying to write an assertion using SVA for the following scenario:

When the signal called ‘valid’ goes HIGH, it results in another signal called ‘alert’ going HIGH 2 or more clock cycles later. The alert signal is eventually cleared by another part of the HW. For each rising edge of valid, I expect to see a rising edge for alert. The assertion I initially wrote was this:

property valid_alert_p(valid, alert);
  @(posedge clk) valid |-> ##[2:$] $rose(alert);
endproperty

This works in most scenarios. However, when a situation arises where alert has not yet been cleared and I see two consecutive rising edges for valid, and then alert is eventually cleared, the very next rising edge on alert causes the assertions for both of those consecutive valid triggers to pass. What I instead want to see is a separate assertion for each pair of valid and alert. I have attached a waveform to demonstrate the problem:

Any help would be appreciated.

Thank you!

[ben2]

In reply to sidmodi:

I address this topic of Uniqueness in attempted threads in my SVA Handbook Basically, need to assure that each started assertion from start to completion is unique; this means that if multiple assertions are started at different cycles because of a successful antecedent, a successful consequent should not terminate all those assertions. Below is a link to those pages from my book that explains the solution.

Uniqueness_v2.pdf

If you have any questions after you read section 10.26 Uniqueness in attempted threads – the FIFO, let me know.

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr

• SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
• A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
• Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
• Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
• Component Design by Example ", 2001 ISBN 0-9705394-0-1
• VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
• VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115

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1. SVA Alternative for Complex Assertions
   Verification Horizons - March 2018 Issue | Verification Academy
2. SVA: Package for dynamic and range delays and repeats | Verification Academy
3. SVA in a UVM Class-based Environment
   SVA in a UVM Class-based Environment | Verification Horizons | Verification Academy

[modisidd]

In reply to ben@SystemVerilog.us:

Thank you! I was able to follow section 10.26 and achieved what I needed to.