Module instantiation depending on input signal

SystemVerilog
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1

Hi,

I want to instantiate a parameterised module in my top module, whoes parameter value changes depending on my input signal, how can I do it?

2

In reply to Abhijitsjadhav:

It is not possible to instantiate a module depending on a input signal.

3

In reply to Abhijitsjadhav:

Hi,
I want to instantiate a parameterised module in my top module, whoes parameter value changes depending on my input signal, how can I do it?

A parameter value can’t change based on input signal. Can you clarify your requirement again?

Regards
Srini
www.verifworks.com

4

In reply to Srini @ CVCblr.com:

Actually I am designing a product which has two models. The code is almost same for these two models, only difference is in top file, one submodule instantiation is different(some parameter changes)in these two model. And that difference is depend on one input signal.
So I was trying to merge these two models code in a single code, where only difference is a submodule instantiation.

5

In reply to Abhijitsjadhav:

Recode it to make that differentiating signal as parameter instead.

Then you can use generate around it. If not you can merge logic inside a single module using if, clumsy code though.

Srini

6

In reply to Srini @ CVCblr.com:

@srini
How to make differentiating signal as parameter. Can you please explain through example.