Sorry for the elementary nature of my question since I am a new systemverilog user.
Reading the Spear book, I came across an example. I am using EDA playground to compile the code. Either of the compilers selected gives me the same result. The example is:
module logic_data_type(input logic rst_h);
parameter CYCLE = 20;
logic q, q_l, d, clk, rst_l;
initial begin
clk = 0;
forever # (CYCLE/2) clk = ~clk;
end
assign rst_l = ~rst_h;
not n1 (q_l, q);
my_dff dl(q, d, clk, rst_l);
endmodule
The error that I get is:
"my_dff dl(q, d, clk, rst_l);"
Module definition of above instance is not found in the design.
Clearly, if I comment out the line in question the code compiles.
What is my issue:
Thank You
Tom