Sorry for the elementary nature of my question since I am a new systemverilog user. Reading the Spear book, I came across an example. I am using EDA playground to compile the code. Either of the compilers selected gives me the same result. The example is: module logic_data_type(input logic rst_h);…

In reply to miner_tom : It would be some thing like this see the definition of dff. [image] EDA Playground Edit, save, simulate, synthesize SystemVerilog, Verilog, VHDL and other HDLs from your web browser.

Module definition of instance not found in the design

SystemVerilog

miner_tom May 4, 2022, 2:37am 4

In reply to rgarcia07:

Please let me know if this comes through

Tom