Module definition of instance not found in the design

SystemVerilog
, ,
2

In reply to miner_tom:

the problem is that d1 is an instance of mv_dff as the error says the definition of that module is not found in the file you compiled, it would be useful to share the EDA playground link.
You need the definition of the module somewhere:

module my_dff (input q...);
...
endmodule

HTH,
-R