Loop

SystemVerilog
,
1

Hello Everyone,

I’ve issues with part of the code I’m working on, please look at the code

task abc_monitor::xyz_monitor();
   forever begin
      @(posedge clk)
            for(int j=0; j<chans; j++) begin
               for(int k=0; k<subchans; k++) begin
                     // code to execute
               end
            end
   //*** assertion check here ***
   end
endtask: xyz_monitor

I’ve two channels and two sub channels (in each channel). At each positive edge of the clock, I need to loop through one channel and one subchannel. In the end, I need to check the assertion. But this code is checking the all the channels, one subchannel and a assertion at one clock.

I need like this:
clk
chan0
subchan0
clk
chan0
subchan1
clk
chan1
subchan0
clk
chan1
subchan1
clk
check the assertion.

2

In reply to naveen23:

Please use code tags to make your code readable. I have added them to your post for you.

Perhaps you want:

task abc_monitor::xyz_monitor();
   forever begin
            for(int j=0; j<chans; j++) begin
               for(int k=0; k<subchans; k++) begin
                      @(posedge clk)
                      // code to execute
               end
            end
   //*** assertion check here ***
   end
endtask: xyz_monitor
3

In reply to dave_59:

Thanks Dave, It’s working :-)