Loop

SystemVerilog
,
2

In reply to naveen23:

Please use code tags to make your code readable. I have added them to your post for you.

Perhaps you want:

task abc_monitor::xyz_monitor();
   forever begin
            for(int j=0; j<chans; j++) begin
               for(int k=0; k<subchans; k++) begin
                      @(posedge clk)
                      // code to execute
               end
            end
   //*** assertion check here ***
   end
endtask: xyz_monitor