Local var assignment in static function

SystemVerilog
1

Hello!

I used following code on ModelSim SE-64 10.0c.

module top_tb;

function static f( input int d_in );
  int d = d_in + 1;

  $display( "d_in = %d", d_in );
  $display( "d    = %d", d    );  
endfunction

initial
  begin
    f( 100 );
  end 

endmodule

I got next output:

> run
# d_in =         100
# d    =           1

Why does “d_in” var is equal to 0 in “d” declaration/initialization line?
Is it correct?

2

In reply to Des333:

Yes.
See 6.8 section of IEEE Std 1800-2012.

3

In reply to Des333:

The code you wrote is illegal to prevent the exact confusion you are experiencing. It should have generated a compiler error. [Edit: this code was legal for a short time in the IEEE 1800-2005 LRM]

Variables declared in a static task, function, or procedural block default to a static lifetime and a local scope. However, an explicit static keyword shall be required when an initialization value is specified as part of a static variable’s declaration to indicate the user’s intent of executing that initialization only once at the beginning of simulation.

This is because when in comes to the lifetime of local variables, legacy Verilog has its defaults backwards from almost every other programming language. SystemVerilog fixed this for class methods by making all local variables automatic by default, but could not change the behavior of legacy Verilog code.

Also see

https://verificationacademy.com/content/re-when-should-be-program-block-dynamic-or-static-members-static-program-block-members-automatic-program-blocks

4

In reply to dave_59:

Thanks!

5

In reply to Des333:

For static task and function , you can refer to the following link

http://www.amiq.com/consulting/2016/08/05/gotcha-static-functiontask-in-systemverilog/

6

In reply to kddholak:

The code in that example has also been made illegal. Class methods always have an automatic lifetime and you cannot change that.