Leading clock mismatch error in a multi-clock property

SystemVerilog
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3

In reply to ben@SystemVerilog.us:

Hi Ben. Even though I used ##0, it is still having the same error.
But when I use ##1, the compilation is good.


  logic clk_A, clk_B, clk_C, sig_Aa, sig_Ab, sig_Ba, sig_Bb, sig_Ca, sig_Cb;
  
  sequence s_seqA(logic clk, a, b);
    @(posedge clk)
    a ##1 b;
  endsequence : s_seqA
  
  sequence s_seqB(logic clk, a, b);
    @(posedge clk)
    a ##1 b;
  endsequence : s_seqB
  
  sequence s_seqC(logic clk, a, b);
    @(posedge clk)
    a ##1 b;
  endsequence : s_seqC
  
  property p_prop(logic clkA, clkB, clkC, sigAa, sigAb, sigBa, sigBb, sigCa, sigCb);
    @(posedge clkA)
    sigAa |-> ##1
    s_seqA(clkA, sigAa, sigAb) ##1 // Replace this with ##0 and it will have an error
    s_seqB(clkB, sigBa, sigBb); 
  endproperty : p_prop
  
  ap_try : assert property(p_prop(clk_A, clk_B, clk_C, sig_Aa, sig_Ab, sig_Ba, sig_Bb, sig_Ca, sig_Cb));