In reply to Reuben:
- @(posedge clkA) sigA |-> @(posedge clkB) sigB; // IS LEGAL
- my_seqA(clkA, sigA) ##5 my_seqB(clkB, sigB);
Violates 1800’2012 16.13.1 Multiclocked sequences, see below
module top;
bit clk1, clk2, a, b, c, d;
initial forever #10 clk1=!clk1;
initial forever #13 clk2=!clk2;
sequence s1;
a ##1 b;
endsequence
sequence s2;
c ##1 d;
endsequence
ap_illegal1_qq: assert property(@(posedge clk1) a ##1 b ##2 @(posedge clk2) s2);
// 1800'2012 16.13.1 Multiclocked sequences
// Differently clocked or multiclocked sequence operands cannot be combined
// with any sequence operators other than ##1 and ##0.
// For example, if clk1 and clk2 are not identical, then the following are illegal:
ap_illegal1: assert property(@(posedge clk1) s1 ##2 @(posedge clk2) s2);
ap_illegal2: assert property(@(posedge clk1) s1 intersect @(posedge clk2) s2); // line 19
// Directive 'ap_illegal2' has multiple leading clocks for its maximal property.
endmodule
// A compiler at eda playground
ERROR ACOMP3007 "Invalid delay operator. Only ##0 and ##1 are supported in multiclock context." "testbench.sv" 12 62
ERROR ACOMP3007 "Invalid delay operator. Only ##0 and ##1 are supported in multiclock context." "testbench.sv" 17 53
ERROR ACOMP3008 "Intersect is not valid multiclocked sequence operator." "testbench.sv" 18 53
Ben Cohen
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- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
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