It seems there is something wrong with'##2 rtr_io.cb.reset_n <= 1'b1' in Test Program since compiling tool sends error that 'a default clocking block must be specified to use the ##n timing statement'. Can someone help to correct the test program? Thx!

As entitled, something wrong with the cycle delay statement.
Could someone help correct the test program.

Many thanks!

Testbench code :
interface router_io(input bit clock);
logic reset_n;
logic [15:0] din;
logic [15:0] frame_n;
logic [15:0] valid_n;
logic [15:0] dout;
logic [15:0] valido_n;
logic [15:0] busy_n;
logic [15:0] frameo_n;

clocking cb @(posedge clock);
default input #1ns output #1ns;
output reset_n;
output din;
output frame_n;
output valid_n;
input dout;
input valido_n;
input busy_n;
input frameo_n;
endclocking: cb

modport TB (clocking cb, output reset_n);

endinterface: router_io

//test program
module automatic test (router_io.TB rtr_io);
initial begin

task reset();
rtr_io.reset_n = 1’b0;
rtr_io.cb.frame_n <= '1;
rtr_io.cb.valid_n <= '1;
##2 rtr_io.cb.reset_n <= 1’b1;// compiling tool tells there is error right here about the ##2 cycle delay statement. NEED GET IT CORRECT
repeat(15) @(rtr_io.cb);
endtask: reset

endmodule: test

`timescale 1ns/100ps

module router_test_top;
parameter simulation_cycle = 100;

bit SystemClock;

router_io top_io (SystemClock);

test t (top_io);

router dut(
.reset_n (top_io.reset_n),
.clock (top_io.clock),
.din (top_io.din),
.frame_n (top_io.frame_n),
.valid_n (top_io.valid_n),
.dout (top_io.dout),
.valido_n (top_io.valido_n),
.busy_n (top_io.busy_n),
.frameo_n (top_io.frameo_n)

initial begin
SystemClock = 0;
forever begin
SystemClock = ~SystemClock;


DUT code:
// control pins:
// input: reset_n - active low reset
// input: clock - master clock input

// input port pins:
// input: frame_n - must be active during whole input packet
// input: valid_n - valid data input
// input: di - the data input
// output: busy_n - tells input that connection is busy

// output port pins:
// output: do - the data output
// output: valido_n - tells output device that “do” contain valid data
// output: frameo_n - active during the whole output packet
// frame format:
// Frame start must look like this:
// frame_n: | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | …
// di: | X | A0 | A1 | A2 | A3 | 1 | X | X | X | D0 | …
// valid_n: | X | X | X | X | X | X | 1 | 1 | 1 | 0/1 | …
// note1: frame_n must deasserted at least one cycle between packets.
// note2: address data does not have to wait for busy_n = 1.
// note3: di must wait for busy_n = 1.
// note4: a di is taken by the chip if: busy_n == 1 && valid_n == 0
// note5: frame_n must be deasserted with the last data bit in the frame.
// note6: once connection is successfully made, busy_n is guaranteed to
// stay inactive until to the end of the current frame.
module router(
reset_n, clock, frame_n, valid_n, din, dout, busy_n, valido_n, frameo_n);

input reset_n, clock;

input [15:0] din, frame_n, valid_n;

output [15:0] dout, valido_n, busy_n, frameo_n;

wire reset;
wire [15:0] arb0, arb1, arb2, arb3, arb4, arb5, arb6, arb7;
wire [15:0] di;
wire [15:0] arb8, arb9, arb10, arb11, arb12, arb13, arb14, arb15;
wire [15:0] arb_head, okstep;

tri0 [15:0] doint;
tri1 [15:0] valdoint_n, frameoint_n;

reg [15:0] dout, valido_n, frameo_n;
reg [3:0] arb_head_num;

assign di = din;

assign reset = ~reset_n;
assign arb_head = 1 << arb_head_num;

rtslice rts0(reset,clock,frame_n[0],valid_n[0],di[0],
rtslice rts1(reset,clock,frame_n[1],valid_n[1],di[1],

In reply to WenChicken:

You need to change this to

rtr_io.cb.reset_n <= ##2 1'b1;


repeat(2) rtr_io.cb;
 @( rtr_io.cb.reset_n <= 1'b1

In reply to dave_59:

Thanks for your professional solution.

I corrected my test program accordingly and it did work!

But how ##2 rtr_io.cb.reset_n <= 1’b1 doesn’t work ? I learned it from the tool book

In reply to WenChicken:

You can have any number of procedural delays before any procedural statement. The procedural delay is unrelated to the procedural statement that follows it.

##2 $display("Hello");

In order for ##2 to work, it needs a default clocking statement in the same scope where it appears.

In reply to dave_59:
But i already have declared ‘clocking cb @(posedge clock);’ in the router_io part.

Isn’t this cb the default clocking statement you mean?

If this is not, what default clocking statement should i declare in this case?

Thanks for reply in advance!