It seems there is something wrong with'##2 rtr_io.cb.reset_n <= 1'b1' in Test Program since compiling tool sends error that 'a default clocking block must be specified to use the ##n timing statement'. Can someone help to correct the test program? Thx!

SystemVerilog
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In reply to dave_59:

Thanks for your professional solution.

I corrected my test program accordingly and it did work!

But how ##2 rtr_io.cb.reset_n <= 1’b1 doesn’t work ? I learned it from the tool book