It seems there is something wrong with'##2 rtr_io.cb.reset_n <= 1'b1' in Test Program since compiling tool sends error that 'a default clocking block must be specified to use the ##n timing statement'. Can someone help to correct the test program? Thx!

SystemVerilog
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2

In reply to WenChicken:

You need to change this to

rtr_io.cb.reset_n <= ##2 1'b1;

or

repeat(2) rtr_io.cb;
 @( rtr_io.cb.reset_n <= 1'b1