HI Dave,
module TOP;
bit reset1,reset2;
//OVM_FILE ch;
ahb_if AHB0(clk,reset1);
ahb_if AHB1(clk,reset2);
// Instantiate PPI Interface
pp_intf ppi0(ppi_clk,reset1);
pp_intf ppi1(ppi_clk,reset2);
endmodule
interface ahb_if(input bit clk, ref bit reset);
...
..
endinterface
interface pp_intf(input bit clk,ref bit reset);
...
..
endinterface
My question is , Is it valid to pass an argument by reference in Interface?
The reason behind doing this is , If i’ll drive a different value of reset on AHB0 instance, It will reflect on ppi0 Instance too,
Thanks.
This is valid from a SystemVerilog syntax point of view, but I’m not sure this will give you the behavior you are looking for. I’m sure you mean more than just having the ahb_if have an output bit reset feed an input bit reset on the pp_intf.
A port passed by reference works just like a task argument passed by reference. The interface instance will indirectly reference the variable it is connected to. So AHB0.reset and ppi0.reset refer to the same variable; reset1. In other words, reset1, AHB0.reset, and ppi0.reset are considered one shared variable. The same assignment rules for variables apply to this shared variable. You are allowed a single continuous assignment to a variable that acts like a driver, or you can have multiple procedural assignments. When you have multiple procedural assignments, there are no drivers, it is simply last write wins.
In reply to dave_59:
Thanks Dave,
I just wanted to know, it is valid valid from a SystemVerilog syntax point of view or Not. It’s working fine as per my requirement.