Is it possible to use SVA syntax inside a system verilog code, outside assertion

SystemVerilog
, ,
1

For instance, could it be possible to use SVA syntax to detect that a signal is high during 10 clock cycles ?

is it possible to use $stable for instance ?

but outside an assertion. inside a process…

2

In reply to iostrym:

You can read section 16.9.3 Sampled value functions, in the 1800-2012 LRM, second paragraph.

3

Thanks a lot, I know this syntax but I only used it inside an assertion.

I wonder if it is possible to use this kind of syntax in a sequential process…

like this :

intial
begin

@(negedge reset);

@($stable(toto))

…

end

because only solution I have currently is to write a for loop, with a counter to count the number of time the signal is stable and if the signal is modified, the counter is reset to 0.

if would be a great facility if the sequence syntax of SVA could be used inside a process.

is it possible ?

4

In reply to iostrym:

Hello There.

You can do something like this.

byte toto;
bit toto_is_stable;

always @(posedge clk) toto=$urandom_range(0,3);
always @(posedge clk) toto_is_stable = $stable (toto);

initial
begin
repeat(5) @(posedge clk);
@(toto_is_stable);
$display ($time);
repeat (5) @(posedge clk);
$finish;
end

5

thanks a lot.

so it means that $stable can be used outside an assertion. in a clocked process then.

if the process is not clocked, like an “initial” or combinational process, is it possible to use “stable” ? using a default clockgroup maybe ?

6

In reply to iostrym:

You can also use SVA syntax inside an expect statement:


expect (
  @(posedge clk)
    ##1 ($stable(some_signal) [*10]) );

This will block for 10 cycles if some_signal is stable or it will issue an error message if this isn’t true and unblock.

Note: the ##1 is in there to have a reference to a previous clock cycle for the first evaluation of $stable(…), otherwise it will be assumed that the first “past” value of some_signal is the default value for that data type.