Is it possible to use SVA syntax inside a system verilog code, outside assertion

Thanks a lot, I know this syntax but I only used it inside an assertion.

I wonder if it is possible to use this kind of syntax in a sequential process…

like this :

intial
begin

@(negedge reset);

@($stable(toto))

end

because only solution I have currently is to write a for loop, with a counter to count the number of time the signal is stable and if the signal is modified, the counter is reset to 0.

if would be a great facility if the sequence syntax of SVA could be used inside a process.

is it possible ?