Is it possible to detect when a signal is 're-written' to the same value?

[jms8]

I have a conceptual question about the way System Verilog works. To make this easy to explain, say that I have code which looks like this:

interface my_interface();
  logic y;

  always @(y) begin
    $display("Activated!");
  end

  task set_y_zero();
    y = 0;
  endtask

  task set_y_one();
    y = 1;
  endtask
endinterface

module test();

  my_interface int();

  initial begin
    int.set_y_zero();
    #10
    int.set_y_zero();  // Location A
    #10
    int.set_y_one();  // Location B
  end

I know from experiments that “Activated!” will be printed when test reaches location B but not location A. However, I would like some way to detect when the task set_y_zero, i.e. “y is written to 0” is called a second time at location A. Unfortunately, all my research seems to indicate that this is impossible; System Verilog events seem to only be scheduled when there is a change. But I would like to confirm:

Is there any way to detect when a variable (logic in this example, but it can be anything) is ‘re-written’ to the same value?

[ben2]

In reply to jms8:

Is there any way to detect when a variable (logic in this example, but it can be anything) is ‘re-written’ to the same value?

If the variable is clocked, you can use the action block or statement to take an action. However, this are restrictions. Also, a reassignment is not necessarily detected. You can tune the assertion or the cover to what you need. For example:

cover property(property_spec) statement_or_null
cp: cover property( @(posedge clk) $rose(v) |=> v[->1]) $display("whatever");  
// If new "v", then another "v" will happen

cp_next1: cover property( @(posedge clk) $rose(v) |=> v) $display("whatever"); 
cp_next0: cover property( @(posedge clk) $fell(v) |=> !v) $display("whatever"); 
 

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

• SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
• A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
• Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
• Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
• Component Design by Example ", 2001 ISBN 0-9705394-0-1
• VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
• VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115

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[ShanyaGupta]

In reply to jms8:

interface my_interface();
logic y;
event e;

always @(e) begin
$display(“Activated!”);
end

task set_y_zero();
y = 0;
->e;
endtask

task set_y_one();
y = 1;
->e;
endtask
endinterface

module test();

my_interface ints();

initial begin
ints.set_y_zero();
#10
ints.set_y_zero(); // Location A
#10
ints.set_y_one(); // Location B
end

endmodule

[ben2]

In reply to shanya:

Is there any way to detect when a variable (logic in this example, but it can be anything) is ‘re-written’ to the same value?

The requirements were for the general case;the above solution requires the application of an event after every set of assignments. It won’t work for variables of type wire.
But it has value.
Ben Ben@systemverilog.us