Is it possible to detect when a signal is 're-written' to the same value?

SystemVerilog
, , , , ,
3

In reply to jms8:

interface my_interface();
logic y;
event e;

always @(e) begin
$display(“Activated!”);
end

task set_y_zero();
y = 0;
->e;
endtask

task set_y_one();
y = 1;
->e;
endtask
endinterface

module test();

my_interface ints();

initial begin
ints.set_y_zero();
#10
ints.set_y_zero(); // Location A
#10
ints.set_y_one(); // Location B
end

endmodule