In reply to jms8:
Is there any way to detect when a variable (logic in this example, but it can be anything) is ‘re-written’ to the same value?
If the variable is clocked, you can use the action block or statement to take an action. However, this are restrictions. Also, a reassignment is not necessarily detected. You can tune the assertion or the cover to what you need. For example:
cover property(property_spec) statement_or_null
cp: cover property( @(posedge clk) $rose(v) |=> v[->1]) $display("whatever");
// If new "v", then another "v" will happen
cp_next1: cover property( @(posedge clk) $rose(v) |=> v) $display("whatever");
cp_next0: cover property( @(posedge clk) $fell(v) |=> !v) $display("whatever");
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
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