Is 'integer' type unsigned by default ? As mentioned in the "SystemVerilog Primer for VHDL Engineers" in "Introduction to the UVM" presented by Ray Salemi

SystemVerilog
1

In this video mentioned that all “Four State Type” data type are unsigned by default.

Link is here:…
But what I know that "integer is 4-state data type and also signed.

can any one explained the difference in both statement? What are the conditions when both statements are right if they ?
‘integer’ is 4-state and signed or it is unsigned.

2

In reply to Anurag Chauhan:

I don’t konw about the video, but of the 4 state types, logic, reg, and time are unsigned by default, and integer is signed by default.

3

In reply to shalom:

Thanks for reply shalom. I am agree with you. I am not blaming on anybody but just want to know… is there any possibility of this type of dual behavior of integer.
Here is snapshot from the lecture…

Supporting doc here…

4

In reply to Anurag Chauhan:

As I read the slide, it is simply incorrect on this point. integer is signed and bit is unsigned.

5

In reply to shalom:

Thanks shalom.