Is 'integer' type unsigned by default ? As mentioned in the "SystemVerilog Primer for VHDL Engineers" in "Introduction to the UVM" presented by Ray Salemi

SystemVerilog
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In reply to shalom:

Thanks for reply shalom. I am agree with you. I am not blaming on anybody but just want to know… is there any possibility of this type of dual behavior of integer.
Here is snapshot from the lecture…

Supporting doc here…