Interface

SystemVerilog
,
1

Hi,

in this program,

“package my_pkg;
import abstract_pkg::;
class driver;
abstract_intf#(16) c_h;
task run;
forever begin
c_h.posedge_clock;
c_h.set_address(‘h1234);
end
endtask
endclass
endpackage
module testTop;
dut_itf #(8,16) i1();
DUT d1(.itf(i1));
TEST t1(.itf(i1));
endmodule
module TEST();
import my_pkg::;
driver d;
initial begin
d = (new);
d.c_h = itf.c;
d.run;
end
endmodule”

what these 2 lines explains,especially #(8,16)
for what # symbol is used.is it time delay…?
abstract_intf#(16) c_h;
dut_itf #(8,16) i1();

and
In interfacing,is there any condition that class should be inside “package”.

2

Interface can have PARAMETERS (like modules).

here doesn’t refer time delay, it is used to override the parameters

Regards,
D

3

In reply to Dilip Bagadi:

In some cases ##(double #) has been used.what is the purpose of that.

4

In reply to R Divyaa:

Can you give the sample code where it is used?

5

In reply to Dilip Bagadi:

##2 arbif.cb.request <= 0;

interface itf #(int width, size);
wire [width

1:0] bus;
logic [7:0] mem[size];
endinterface
module top;
itf #(.width(8),.size(16)) i1();
itf #(.width(16),.size(32)) i2();
endmodule
class monitor;
virtual itf #(#(.width(8),.size(16)) vi
tf1;
virtual itf #(#(.width(16),.size(32)) vitf2;
endclass

6

In reply to R Divyaa:

used for mentioning cycle-delay