In reply to Dilip Bagadi:
##2 arbif.cb.request <= 0;
interface itf #(int width, size);
wire [width
1:0] bus;
logic [7:0] mem[size];
endinterface
module top;
itf #(.width(8),.size(16)) i1();
itf #(.width(16),.size(32)) i2();
endmodule
class monitor;
virtual itf #(#(.width(8),.size(16)) vi
tf1;
virtual itf #(#(.width(16),.size(32)) vitf2;
endclass