Hello Everyone,
I have a Wishbone Compliant IP Master I2C Core and I have its TB as well for inserting the values in its registers in order to activate the core. e.g to send a Start condition, to transmit address, etc. Now i am making a slave driver to verify the core but unfortunately i have found out that firstly I have to initiate the core by setting register values of core. Now, I am really confused that where should I put that TB in my Verification environment. Of course, I cannot put it this TB in my verification component. Should I instantiate my TB in my TOP module? OR should I write my whole TB in TOP Module. Of course I will have to Instantiate the DUT as well in TOP Module.
Any Ideas, Any Suggestions? What do u recommend? Has anyone faced this situation already?
In reply to khnabeel:
You need to create wishbone master environment first.I created a separate class for tests in a task inside that class.This task sends the transactions to driver.Using this class instance,I ran that test task in generator class.
In reply to rajan passionate:
What do u mean? I didn’t completely understood this thing. I don’t want to write Wishbone Interface. I am trying to to use the TB that sets register values in my TOP module. Can you please elaborate more? I will be thankful to you. Do u have any example with you? may b in a block diagram? or somehow?
What I understood is that you made a separate class in test. Now this class sends Seq_items to sequencer? And this sequencer sends those transactions to driver?
In that separate class have u instantiated TB? or u had written wishbone interface? I am really confused.
In reply to khnabeel:
Actually I did in SV only not in UVM.I wrote TB using wishbone interface signals.Can you please elaborate more about your TB?Was it a verilog TB?If not what are the components in your TB ENV?Then I can help you.
In reply to rajan passionate:
Yes, This TB is written in Verilog where we are using WBC signals to set the registers inside IP core. Actually I have to use this TB inside UVM environment. But I am not getting an idea that how can I use that TB inside UVM environment. This TB is driver for that core and only this TB can initiate the core.
In reply to khnabeel:
Until and unless you convert that TB into SV compatible one,it’s difficult to proceed further.
In reply to rajan passionate:
And after converting… What should I do? I mean what will be the further steps? How should I proceed? I am confused that if I have this TB. How can I use this inside UVM environment?
In reply to khnabeel:
First you convert in into task based SV TB and then you will only understand how to do it.If any difficulty, I am there to help.