In reply to khnabeel:
Actually I did in SV only not in UVM.I wrote TB using wishbone interface signals.Can you please elaborate more about your TB?Was it a verilog TB?If not what are the components in your TB ENV?Then I can help you.
In reply to khnabeel:
Actually I did in SV only not in UVM.I wrote TB using wishbone interface signals.Can you please elaborate more about your TB?Was it a verilog TB?If not what are the components in your TB ENV?Then I can help you.