I have instantiated another module (slave_con_assert) in UVM’s top module for Concurrent assertions (Since we cannot use inside any class)
I’m passing DUT-Interface, global CLK and RESET signal to the assertion module.
My query is
Will the ASSERTION-module be updated according to the DUT-interface ??
Can i continue by adding other check points in Concurrent-assertions ??
Is there any other better way to serve my purpose ??
Kindly help me out !!
Thank you!!
For reference I’m attaching my code (not tested) here:
module top();
bit clk;
logic reset=1'b1;
//AHB Bus and Slave Instantiation
ahb_if ahb_top_i(clk, reset); // Interface
ahb_slave2 slave2(ahb_top_i); // DUT
concurrent_assertion slave_con_assert(ahb_top_i, clk, reset); // For the sake of Concurrent Assertions
initial
begin
//Reset condition
#1 reset=0;
ahb_top_i.HTRANS='d0;
ahb_top_i.HADDR=32'b0;
ahb_top_i.HWRITE='b0;
ahb_top_i.HBURST='d0;
ahb_top_i.HSIZE='d0;
ahb_top_i.HWDATA=32'bz;
#10 reset=1;
end
always
#5 clk = ~clk;
initial
begin
uvm_config_db#(virtual interface ahb_if)::set(null,"*","ahb_if",ahb_top_i);
`uvm_info( get_name() ,"start test",UVM_NONE);
run_test("ahb_test");
end
initial begin
$dumpvars();
$dumpfile("ahb.vpd");
end
endmodule:top
interface ahb_if(input clk, input reset);
logic[31:0] HADDR;
logic HWRITE;
logic [2:0] HSIZE;
logic [2:0] HBURST;
logic [1:0] HTRANS;
logic [31:0] HWDATA;
logic HREADY;
logic HRESP;
logic[31:0] HRDATA;
endinterface
module concurrent_assertion (ahb_if ahb_top_i, input clk, input reset);
int basic_burst_write_check_Pass,basic_burst_write_check_Fail;
property basic_burst_write;
@(posedge clk)
disable iff (ahb_top_i.HTRANS == BUSY)
((ahb_top_i.HWRITE==1)&&(ahb_top_i.HTRANS == NON_SEQ) )|=>(ahb_top_i.HREADY=='1) ;
endproperty
assert property(basic_burst_write)
begin
basic_burst_write_check_Pass++;
end
else
begin
basic_burst_write_check_Fail++;
end
final
begin
$display( " basic_burst_write_check\t\t%d\t\t%d\t\t%d ", (basic_burst_write_check_Pass+basic_burst_write_check_Fail),basic_burst_write_check_Pass,basic_burst_write_check_Fail);
end
endmodule
I have instantiated another module (slave_con_assert) in UVM’s top module for Concurrent assertions (Since we cannot use inside any class)
I’m passing DUT-Interface, global CLK and RESET signal to the assertion module.
My query is
Will the ASSERTION-module be updated according to the DUT-interface ??
[Ben] Absolutely YES.
Can i continue by adding other check points in Concurrent-assertions ??
[Ben] Absolutely YES.
Is there any other better way to serve my purpose ??
You can put assertions inside interfaces. You can also copy from UVM needed variables declared in the classes into interface variables, and use those interface variables in your assertions.
You can also write assertions inside checkers and bind the checkers to interfaces and modules. I also explain the use of checkers in my SVA book.
You can use default clockings and defaults resets instead of declaring the clocking event and disables in your assertions. For example:
Use the UVM severity levels instead of $displays in you action blocks. For example:
ap_LOW: assert property(a) else
`uvm_info(tID,$sformatf("%m : error in a %b", a), UVM_LOW); // Line 9
ap_MEDIUM: assert property(a) else
`uvm_info(tID,$sformatf("%m : error in a %b", a), UVM_MEDIUM); // Line 11
ap_HIGH: assert property(a) else
`uvm_info(tID,$sformatf("%m : error in a %b", a), UVM_HIGH); // Line 13
ap_FULL: assert property(a) else
`uvm_info(tID,$sformatf("%m : error in a %b", a), UVM_FULL); // Line 15
ap_test2: assert property(a) else
`uvm_error(tID,$sformatf("%m : error in a %b", a)); // Line 17