Input needed: Assertion module initiated from UVM's Top module

SystemVerilog
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In reply to vvv:

I have instantiated another module (slave_con_assert) in UVM’s top module for Concurrent assertions (Since we cannot use inside any class)
I’m passing DUT-Interface, global CLK and RESET signal to the assertion module.
My query is

  1. Will the ASSERTION-module be updated according to the DUT-interface ??

[Ben] Absolutely YES.

  1. Can i continue by adding other check points in Concurrent-assertions ??

[Ben] Absolutely YES.

  1. Is there any other better way to serve my purpose ??

[Ben]

  1. I recommend that you read my paper entitled SVA in a UVM Class-based Environment
    located in
    https://verificationacademy.com/verification-horizons/february-2013-volume-9-issue-1/SVA-in-a-UVM-Class-based-Environment
  2. You can put assertions inside interfaces. You can also copy from UVM needed variables declared in the classes into interface variables, and use those interface variables in your assertions.
  3. You can also write assertions inside checkers and bind the checkers to interfaces and modules. I also explain the use of checkers in my SVA book.
  4. You can use default clockings and defaults resets instead of declaring the clocking event and disables in your assertions. For example:
default clocking cb_clk @ (posedge clk); endclocking
default disable iff (rst);
  1. Use the UVM severity levels instead of $displays in you action blocks. For example:
ap_LOW: assert property(a) else
`uvm_info(tID,$sformatf("%m : error in a %b", a), UVM_LOW); // Line 9
ap_MEDIUM: assert property(a) else
`uvm_info(tID,$sformatf("%m : error in a %b", a), UVM_MEDIUM); // Line 11
ap_HIGH: assert property(a) else
`uvm_info(tID,$sformatf("%m : error in a %b", a), UVM_HIGH); // Line 13
ap_FULL: assert property(a) else
`uvm_info(tID,$sformatf("%m : error in a %b", a), UVM_FULL); // Line 15
ap_test2: assert property(a) else
`uvm_error(tID,$sformatf("%m : error in a %b", a)); // Line 17

Other papers that might be of interest to you of interest to you.
See my White paper: “Using SVA for scoreboarding and TB designs”
http://SystemVerilog.us/papers/sva4scoreboarding.pdf
and a related issue at the Verification Academy the following paper
“Assertions Instead of FSMs/logic for Scoreboarding and Verification”
available in the verification-horizons October-2013-volume-9-issue-3
http://verificationacademy.com/verification-horizons/october-2013-volume-9-issue-3
and “SVA in a UVM Class-based Environment”
https://verificationacademy.com/verification-horizons/february-2013-volume-9-issue-1/SVA-in-a-UVM-Class-based-Environment

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

  • SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
  • A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
  • Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
  • Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
  • Component Design by Example ", 2001 ISBN 0-9705394-0-1
  • VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
  • VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115