Inout port illegal connection error

UVM
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4

In reply to nrllhclb:

See here an example:

module des(input logic a, output logic b, inout wire c);

endmodule

interface intf();
  logic x;
  logic y;
  wire z;
  //logic z;
endinterface

module top();

intf iface();
des DUT(.a(iface.x), .b(iface.y), .c(iface.z));
endmodule

Replacing the wire in the interface with logic results in the error message:
inout.sv(15): Illegal inout port connection for ‘c’ (3rd connection).