Can anyone explain me what is the difference in Including and Instantiating?
In reply to Ayush:
If by including you mean using the SystemVerilog
`include construct, and by instanciating you mean the creation of a module instance or class object, there two constructs have nothing to do with each other. `include is used with macros and ifdef’s to for the stream of text that gets read as a compilation unit. There is no understanding of any SystemVerilog source text syntax
In reply to dave_59:
By include by i mean, 'include “file_name.sv” and by instantiating i mean, as we do in verilog,design instantiating in testbench ?
In reply to Ayush:
Including as you’ve defined it simply means copy the text from file_name.sv and paste it where `include is called. It is part of the preprocessor and happens before the design is compiled. As Dave mentioned,
There is no understanding of any SystemVerilog source text syntax
.
When you instantiate a design, you’re creating a new instance of a defined module. This is where the syntax is actually understood.
You might `include files into the module definition:
module a(
`include "a_port_list.my_extension"
);