In reply to dave_59:
By include by i mean, 'include “file_name.sv” and by instantiating i mean, as we do in verilog,design instantiating in testbench ?
In reply to dave_59:
By include by i mean, 'include “file_name.sv” and by instantiating i mean, as we do in verilog,design instantiating in testbench ?