Import C Task not getting completed and blocking SV test

SystemVerilog
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1

I have created a test which calls DPIC import task, the task is called from UVM test, the task is performing the operation correctly but is not getting ended after completion of its operation. Which indeed is blocking UVM test to perform other operations.

The DPIC import task is called with contect and consumes time. This task also calls multiple export task and function in my UVM testbench.

I am confused why this DPIC import task is not getting ended and blocking my further program?

2

In reply to meet81193:

Without posting any code, it is impossible to provide an answer.

3

In reply to meet81193:

You also need to tell us when it the task should have ended. Did you mean to fork the imported task into a separate process with fork/join_none?

4

In reply to cgales:
Sure, So below i have written a gist of my code. It doesn’t specify tomuch details but i hope it would make sense.

I have a uvm_test which calls 2 import task run_PowerOnSeq_test and run_StartTraining_test.
uvm_test:

class test extends uvm_test;

  task main_phase(uvm_phase phase);
    run_PowerOnSeq_test();
    `uvm_info("My Power Sequence is completed");
    run_StartTraining_test();
    `uvm_info("My Training Sequence is completed");
  endtask
endclass

Inside package adding few DPI import and exports as listed below.
DPI Pkg:

package api_pkg;
  
  // DPI Access
  // DPI exports:
  export "DPI-C" task c_reg_write;
  export "DPI-C" task c_reg_read;
  export "DPI-C" task c_wait_1us;

  
  // DPI imports:
  // This task has to be called in the SystemVerilog to
  // start the c side of things
  import "DPI-C" context task run_PowerOnSeq_test();
  import "DPI-C" context task run_StartTraining_test();
endpackage

This C test cases defines import task and calls export tasks like writing/reading register and waiting for some dealy. both of the import task is in same c test file.
C Test Case:

void run_PowerOnSeq_test(); {
  c_write_reg();
  c_wait_1us();
  c_reg_read():
  print_info("C: Power On Seq is Completed");
}

void run_StartTraining_test(); {
  c_write_reg();
  c_wait_1us();
  c_reg_read():
  print_info("C: Start Training is Completed");
}

Output Log:
C: Power On Seq is Completed

The issue which is happening is my test is completing run_PowerOnSeq_test but C task is not getting ended somehow. Therefore my UVM test is blocked in my first C task.

5

In reply to dave_59:
Have not used any fork on the import task. Import C task should get ended as soon as the program inside the C task is completed.

6

In reply to meet81193:

The code you have shown looks OK. There is probably something wrong with the code you have not shown.

7

In reply to dave_59:

Is it possible that simulator is not returning to SV from C if I am calling export task with wait and delay, in an import task.

8

In reply to meet81193:

You do not show what print_info does, but if the last line is a printf statement displaying “C: Power On Seq is Completed” and the next statement after calling run_PowerOnSeq_test(); is `uvm_info(“My Power Sequence is completed”);, then I cannot explain what is wrong. I suggest using your tool’s debugger to single step through the code.