Import C Task not getting completed and blocking SV test

SystemVerilog
, , ,
4

In reply to cgales:
Sure, So below i have written a gist of my code. It doesn’t specify tomuch details but i hope it would make sense.

I have a uvm_test which calls 2 import task run_PowerOnSeq_test and run_StartTraining_test.
uvm_test:

class test extends uvm_test;

  task main_phase(uvm_phase phase);
    run_PowerOnSeq_test();
    `uvm_info("My Power Sequence is completed");
    run_StartTraining_test();
    `uvm_info("My Training Sequence is completed");
  endtask
endclass

Inside package adding few DPI import and exports as listed below.
DPI Pkg:

package api_pkg;
  
  // DPI Access
  // DPI exports:
  export "DPI-C" task c_reg_write;
  export "DPI-C" task c_reg_read;
  export "DPI-C" task c_wait_1us;

  
  // DPI imports:
  // This task has to be called in the SystemVerilog to
  // start the c side of things
  import "DPI-C" context task run_PowerOnSeq_test();
  import "DPI-C" context task run_StartTraining_test();
endpackage

This C test cases defines import task and calls export tasks like writing/reading register and waiting for some dealy. both of the import task is in same c test file.
C Test Case:

void run_PowerOnSeq_test(); {
  c_write_reg();
  c_wait_1us();
  c_reg_read():
  print_info("C: Power On Seq is Completed");
}

void run_StartTraining_test(); {
  c_write_reg();
  c_wait_1us();
  c_reg_read():
  print_info("C: Start Training is Completed");
}

Output Log:
C: Power On Seq is Completed

The issue which is happening is my test is completing run_PowerOnSeq_test but C task is not getting ended somehow. Therefore my UVM test is blocked in my first C task.