Implementing the assertions API in the uvm environment

SystemVerilog
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1

Hello All,

I was going through the LRM section 40.5.3 Obtaining coverage information ,and i wanted to know ,how these API’s can be imported to our UVM testbench.

Please let me know do i need to import any sva packages ?.
Thanks,
vinay

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This chapter is meant as a C API for tool developers to analyze coverage data. Although it is possible to import this API into SystemVerilog, it is not the intended purpose. It might help for you to explain in more detail what you information you are looking to get.

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Thanks Dave, Will look into the content thats been pointed out here.