I want to constrained random 10 bit such that there won't be 7 consecutive 0s or 1s. Can someone suggest anything ? Thanks in advance

SystemVerilog
,
3

In reply to dave_59:

parameter width = 7;

constraint c_data
{
    foreach(data[i]) 
    {
        (i < data.size() - width) -> !(data[i+:width] inside {'0,'1};
    }
}