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I want to constrained random 10 bit such that there won't be 7 consecutive 0s or 1s. Can someone suggest anything ? Thanks in advance
SystemVerilog
systemverilog-arrays-struct-constraint-randomization-indexes
,
SystemVerilog
dave_59
February 8, 2021, 3:36pm
2
In reply to
jigar123
:
You might want to look at
this
or
this
for ideas.
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