How UVM's TLM matches TLM standards

Hi,
I have a questions about tlm:
TLM_1 and TLM_2 standards are fully supported in UVM library?
If answer is no, then what features aren’t supported?
How to write tlm models using only UVM?

I don’t know SystemC and TLM examples written on it I can’t understand. There are only few TLM examples I know written on systemverilog using UVM, but they are rather weak. Does some cookbook/tutorial exist?

Regards,
Albert

The answer to this question is complex. The SystemC TLM standards were designed for use in a C++ environment using a SystemC library; they were never intended to be used in other languages. But you can still take many of the concepts, terminology, and methodologies from TLM and apply it to many other modeling environments.

It just so happens that the history of the UVM comes from many contributions, and one of those contributions (the AVM) was developed by some of the same people who developed the TLM 1.0 standard for SystemC. They put as much TLM as they could into the AVM, which was transferred to the OVM, and later the UVM.

You can learn about using TLM with UVM is this course: How TLM Works | Advanced UVM | UVM/OVM Verification Methodology | Verification Academy

I would say that most people today use TLM not just for within the UVM, but to interact with SystemC models.

If UVM doesn’t fully support TLM standards I may encounter some challenges when developing TLM-model.

The course doesn’t answer the questions:

  1. How to implement one_to_many/many_to_one/many_to_many relations between components?
  2. May I use analysis_fifo, analysis_port and analysis_export for device modeling besides analysis?
  3. The only way to synchronize initiator and target run_phase threads are UVM_TLM_FIFO and UVM_TLM_*_CHANNEL, aren’t it?
  4. Can TLM_2 features fully substitute TLM_1?
  5. How should transition from specification to TLM-Model be made?
  6. Can any functionality described in the TLM standards be implemented using systemverilog and UVM features?

Regards,
Albert

In reply to dave_59:

Dave,

I would say that most people today use TLM not just for within the UVM, but to interact with SystemC models.

How most people write TLM-models using systemverilog?
Should I learn to SystemC in order to write TLM-model?

In reply to Fitc:

It would help to know your motivation for looking into TLM in the first place.

In reply to dave_59:

A design have requirements on bitrate, memory and time. It will contain third party’s devices. Design doesn’t utilize software. It will be implemented mainly using FPGA. TLM-model should answer the following questions:
How do third party’s devices operate?
How much memory are required?
How many links are required?
Is it correct architecture?
What should be refined?
Does design match bitrate requirements?
How long design executes task?
etc.