How UVM's TLM matches TLM standards

SystemVerilog
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If UVM doesn’t fully support TLM standards I may encounter some challenges when developing TLM-model.

The course doesn’t answer the questions:

  1. How to implement one_to_many/many_to_one/many_to_many relations between components?
  2. May I use analysis_fifo, analysis_port and analysis_export for device modeling besides analysis?
  3. The only way to synchronize initiator and target run_phase threads are UVM_TLM_FIFO and UVM_TLM_*_CHANNEL, aren’t it?
  4. Can TLM_2 features fully substitute TLM_1?
  5. How should transition from specification to TLM-Model be made?
  6. Can any functionality described in the TLM standards be implemented using systemverilog and UVM features?

Regards,
Albert