How to write constraint to generate incremental 4 byte aligned addresses

SystemVerilog
1

could you please help me with the following clarification

there is a memory which can take addresses 0x00 to 0x100 except the reserved memory. reserved memory is 0x20 to 0xE0. address should not take reserved memory. address should be 4 byte aligned memory . how to write a constraint such that it generates 16 byte addresses. for example if it generates 0x0 now it should generate 0x4 ,next 0x8 next 0x12 addresses. I have written 3 constraints. how to write constraint such that it generates 16byte addresses.


class exa;
rand bit [31:0] addr;

constraint con1 { addr inside {[0x0:0x100]};}
constraint con2 { !addr inside {[0x20:0xE0]};}
constraint con3 { addr[1:0]==0 ;}

endclass
2

In reply to srbeeram:

You can create a counter that gets incremented in post_randomize

class exa;
  rand bit [31:0] addr;
  bit [2:0] counter;
 
  constraint con1 { counter == 0 -> addr inside {['h0:'h100]};}
  constraint con2 { counter == 0 -> ! (addr inside {['h20:'hE0]} ) ;} // ! has higher precedence than inside
  constraint con3 { addr[1:0]==0 ;}
  constraint con4 { counter != 0 -> addr == const'(addr+4) ; }

  function void post_randomize();
    if (counter++==4) counter =0;
  endfunction
endclass

You will have to adjust the range constraints so that the series does not overlap. If 'h100 is a valid starting address, is 'h104 also valid?

3

In reply to dave_59:

Hi Dave,
Thank for the clarifications. 'h104 is not valid address.

4

In reply to dave_59:

Hi,
based on the code i think there might be a possibility of getting address between 'h20:'hE0 if initial address = 'h18 or 'h14, but in the question statement “reserved memory is 0x20 to 0xE0. address should not take reserved memory.” so how to avoid this?

plz correct me if i am wrong here

5

In reply to Desam:

That is what I meant by “adjust the range constraints”. So the reserved memory range should be 'h10:'hE0