How to write constraint to generate incremental 4 byte aligned addresses

SystemVerilog
2

In reply to srbeeram:

You can create a counter that gets incremented in post_randomize

class exa;
  rand bit [31:0] addr;
  bit [2:0] counter;
 
  constraint con1 { counter == 0 -> addr inside {['h0:'h100]};}
  constraint con2 { counter == 0 -> ! (addr inside {['h20:'hE0]} ) ;} // ! has higher precedence than inside
  constraint con3 { addr[1:0]==0 ;}
  constraint con4 { counter != 0 -> addr == const'(addr+4) ; }

  function void post_randomize();
    if (counter++==4) counter =0;
  endfunction
endclass

You will have to adjust the range constraints so that the series does not overlap. If 'h100 is a valid starting address, is 'h104 also valid?