How to use wild card (.*) port connection?

SystemVerilog
1

Dear All,

I found some article for port connection by using (.*) wildcard in systemverilog.
https://verificationacademy.com/forums/systemverilog/wildcard-port-connections-systemverilog/verilog

Let’s say we have the module as follow,

module my_mod (
   input         clk,
   input         ctl_in,
   input [7:0]   data_in,
 
   output        ctl_out,
   output [15:0] data_out
);

basically, I instantiate it as below,


wire w_clk;
wire wctl_in;
wire w_data_in;
wire w_ctl_out;
wire w_data_out;

my_mod u_my_mod(
.clk(w_clk),
.ctl_in(w_ctl_in),
.data_in(w_data_in),
.ctl_out(w_ctl_out),
.data_out(w_data_out),

but I found wild card port connection style.


my_mod u_my_mod(
.*
);

If it has instantiated as wildcard style. how do I know connection between relationship information such as clk is connected w_clk we know, but don’t know in wildcard style.?
how do I which signal is connected into ?

Could you guide me with simple example for understanding?

2

In reply to UVM_LOVE:

From section 23.3.2.4 of the LRM:
SystemVerilog can implicitly instantiate ports using a .* wildcard syntax for all ports where the instance port name matches the connecting port name and their data types are equivalent.

You need to have connections that match names and data types. Since ‘w_clk’ and ‘clk’ aren’t the same name, they won’t be connected. You need to declare ‘wire clk’.

3

In reply to cgales:

In reply to UVM_LOVE:
From section 23.3.2.4 of the LRM:
SystemVerilog can implicitly instantiate ports using a .* wildcard syntax for all ports where the instance port name matches the connecting port name and their data types are equivalent.
You need to have connections that match names and data types. Since ‘w_clk’ and ‘clk’ aren’t the same name, they won’t be connected. You need to declare ‘wire clk’.

Thank you Sir, I got clearly your answer.
I declared as below and I got no error.

  
  logic  [3:0] a	;
  logic  [3:0] b	;
  logic  [6:0] c        ;
  
  logic  [3:0] a0	;
  logic  [3:0] b0	;
  logic  [6:0] c0       ;
  //...

  adder DUT (  
   .*
  );

BTW, How do I access a,b,c signal in class if I use(.*) wildcard port connection?
Would you please share with me your idea please?