Hi,
When we instantiate a module we connect the signals using wildcard named port connections.
Lets say we have the following module.
module my_mod (
input clk,
input ctl_in,
input [7:0] data_in,
output ctl_out,
output [15:0] data_out
);
We instantiate it as follows.
my_mod inst1(.*);
Is there a construct in systemverilog/verilog to connect all the input nets using wildcard and leave all outputs open?
something like
my_mod inst_special(.*, .output(open));
Thanks,
Sunil.