In reply to UVM_LOVE:
From section 23.3.2.4 of the LRM:
SystemVerilog can implicitly instantiate ports using a .* wildcard syntax for all ports where the instance port name matches the connecting port name and their data types are equivalent.
You need to have connections that match names and data types. Since ‘w_clk’ and ‘clk’ aren’t the same name, they won’t be connected. You need to declare ‘wire clk’.